Cadence Tutorial
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Overview
In this module you will perform an extraction of your cell. This process will generate a detailed description of the circuit (netlist) that includes the parasitic resistances and capacitances associated with the individual transistors as well as the interconnections. This will allow a more realistic simulation than we we able to do using just the schematic, since it ignored everything except the behavior of the isolated transistors.Extraction
Save your layout.To begin extraction, select Verify->Extract
The extractor will pop-up. Click on 'Set Switches' and select Extract_parasitic_caps. If we didn't set this we would get the same result that we got using the schematic and this would be pointless. Since we don't have any instances of other cells we can leave the ectract method on 'flat.' Click OK and check the CIW for the results. This could take a few minutes.
You will see a list of the transistors and capacitors that the extractor identified. Check it out and see if it makes sense. Do you have the number of nmos and pmos that you expected?
Layout versus Schematic
Open the extracted cellview in Virtuoso. It will look similar to the layout except that only the pins will appear as solid rectangles. Also, you will see symbols representing the extracted nmos, pmos and capacitors.Now we will compare the layout and the schematic to ensure that they are functionally equivalent circuits. Cadence has a tool that will compare the netlist generated by the extraction with a schematic.
Select Verify->LVS
The LVS window will open as well as an 'LVS Form Contents' window. Ensure that the box marked 'form contents' is checked in the second window. In the LVS window, ensure that both the schematic and extracted cells are listed correctly. The other defult options should be sufficient. Click Run. After a couple minutes you should get a messge that the job succeeded. This doesn't mean your netlists matched, only that the checker ran without error.
Click 'Output' to view the results.
The file should say that the netlists match. If not, you may need to change your layout to match your schematic, but first, you should check to ensure that the pin names match in both files as this is a common error.